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- Design, implementation and documentation of complex design and verification environments (UVM)
- Code documentation (e.g. with natural docs)
- IP/Block- & system level testbench development
- Verification component (VC) development for in-house protocols and integration of suppliers VIPs (System-VC, GPIO-VC,…)
- Register and memory model based API for abstraction and reuse
- Reference model development and integration (C/C++/SystemC)
- Advanced Scoreboarding
- Verification planning and management from requirements design to completion
- Coverage-driven Constraint Random Verification (CRV)
- Maintenance and support
- Specman e to System Verilog migration
